Tampilkan postingan dengan label 7 Segment. Tampilkan semua postingan
Tampilkan postingan dengan label 7 Segment. Tampilkan semua postingan

Selasa, 15 Juni 2010




Introduction
In this experiment you will demonstrate the operation of a decoder-driver circuit that accepts a binary or BCD input code and generates the 7 segment display signals to produce the numbers 0 through 9 and other characters.
Figure 1 shows a simplified block of the 74LS48 BCD to 7-Segment Decoder. The 74LS48 contains three main block circuits, a 7-segment decoder, a driver and a system of basic memory units. The basic memory unit is often called a latch or a flip-flop. The decoder outputs drive an encoder circuit made up of OR gates that generate the 7-segment code necessary to display the digits 0 through 9 and the letters a through f. The output devices are current driver transistors that supply the proper current to th e segments in the driver.




Figure 1





Equipment needed
    Microprocessor power supply
    Logic Probe
    74LS00
    74LS02
    74LS04
    74LS48 (46)
    7-Segment LED




Figure 2
Part 1. -- Set-Reset flip-flop
  1. Wire the latch circuit shown in fiqure 2. The Set (A) and Reset (B) are the inputs and C (L1) and C (L2) are the outputs.
  2. Apply power to the circuit and create a truth table for S and R Inputs and C and C outputs.
  3. Wire the latch circuit shown in figure 3. Repeat steps 1. and 2. for circuit 3. These new outputs are labeled D and D. Why do we call this circuit a basic memory unit? What happens to the outputs when S and R both 0? Refer to the textbook (Katz) for a discussion of flip-flops (chapter 6).
Part 2. -- (7-Segment Decoder-Driver and Display)
  1. Construct the circuit shown in figure 4. Use the TTL handbook to verify the correct conections. The pin connections for the 74LS48 and the 7-Segment Display are shown in fiqure 5.
  2. Calculate the value of the resistor between the 74LS48 and the 7-seg LED.
  3. Apply power to the circuit. Create a truth table for figure 4. Do the LEDs L1-L4 which output the binary word agree with the output of the 7-Segment LED? What does the 7-Segment LED read in binary states 1010-1111? What do you think the LT, RBI and BI/ RBO pins do?
Figure 3
Figure 4
Figure 5
Check the MAN74A documentation.
Seven segment display   7-Segment Displays
Truth Table to Decode Binary into 7-Segment



Decimal
Number
Inputs Outputs
DCBA abcdefg
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
0
1
1
01
1
1
1
1
1
1
1
1
10
0
1
1
1
1
1
0
1
11
1
1
1
1
1
0
1
1
01
1
0
1
1
1
0
1
0
00
1
0
1
0
1
0
0
0
11
1
0
1
1
0
0
1
1
11
1
0
1
1






Layout of 7-segment display 


Karnaugh Mapping for Segment a:
The Truth Table:

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx
Boxing ones:

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx

Red cells are represented by B; this is a 4x2 supercell.

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx

Green cells are represented by D; this is a 2x4 supercell.
So far then we have:

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx

where grey boxes indicate cells included in more that one supercell. The shaded boxes are represented by B+D.
Focusing on the remaining cells with ones:

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx

Blue cells are represented by A.C; this is a 2x2 supercell.

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx

Cyan cells are represented by A'.C'; this is a 2x2 wrap-around supercell.

BA 00  01  11  10 
DC\
 00 1011
 01 0111
 11 xxxx
 10 11xx

All cells are represented by B + D + A.C + A'.C', as shown for segment a.
Karnaugh Mapping for Segment c:
The Truth Table:

BA 00  01  11  10 
DC\
 00 1110
 01 1111
 11 xxxx
 10 11xx
Boxing zeroes:

BA 00  01  11  10 
DC\
 00 1110
 01 1111
 11 xxxx
 10 11xx

The red cells are represented by C'.B.A'; of course the complement is required for the final realization. Thus (C'.B.A')' is the combination of gates that is realized from the Karnaugh mapping of zeroes. Application of De Morgan's theorem results in the combination of gates shown for segment c:
(C'.B.A')' = C + B' + A

Seven segment display   Decoder for segment a
Layout of 7-segment decoder
DCBA a
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
0
1
1
01
1
1
1
1
       
Seven segment display   Decoder for segment b
Layout of 7-segment decoder
DCBA b
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
1
1
1
10
0
1
1
1
Seven segment display   Decoder for segment c
Layout of 7-segment decoder
DCBA c
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
1
0
1
11
1
1
1
1
       
BA 00  01  11  10 
DC\
 00 1110
 01 1111
 11 xxxx
 10 11xx

Karnaugh
Seven segment display   Decoder for segment d
Layout of 7-segment decoder
DCBA d
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
0
1
1
01
1
0
1
1
Seven segment display   Decoder for segment e
Layout of 7-segment decoder
DCBA e
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
0
1
0
00
1
0
1

BA 00  01  11  10 
DC\
 00 1001
 01 0001
 11 xxxx
 10 10xx
 

Seven segment display   Decoder for segment f
Layout of 7-segment decoder
DCBA f
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
1
0
0
0
11
1
0
1
1
 

Seven segment display   Decoder for segment g
Layout of 7-segment decoder
DCBA g
0
1
2
3
45
6
7
8
9
0
0
0
0
00
0
0
1
1
0
0
0
0
11
1
1
0
0
0
0
1
1
00
1
1
0
0
0
1
0
1
01
0
1
0
1
0
0
1
1
11
1
0
1
1

Rabu, 06 Februari 2008

PERCOBAAN 3
DISPLAY 7 SEGMEN


TUJUAN:
1. Siswa memahami rangkaian interface mikrokontroller dengan 7 segmen
2. Siswa dapat memahami program assembly untuk menampilkan data ke 7 segment
3. Siswa memahami beberapa instruksi assembly dasar, MOV, Setb, Clr, dan waktu tunda.